The present invention relates to a decoder and, more particularly, to a decoder of the type decoding, among others, equivalently high-rate codes which are produced by deleting codes bits at particular positions of a time sequence of low-rate convolutional code symbols by maximum likelihood decoding.
In communications art, an error correcting system which is the combination of convolutional coding and maximum likelihood decoding is available in order to correct transmission errors ascribable to a digital transmission path and thereby to enhance quality transmission. The error correcting capability of such a system increases with the decrease in coding rate (increase in redundancy) and with the increase in code constraint length. An increase in coding rate results in an increase in the number of bits of code symbols. On the other hand, the hardware of a Viterbi decoder or similar decoder using maximum likelihood decoding is exponentially scaled up as the number of bits of code symbols and the constraint length become greater, as well known in the art. For a radio transmission path whose available frequency band is severely limited, it is preferable to increase the coding rate to thereby reduce the redundancy on the path as far as possible and, yet, to adopt an error correcting system having a high error correcting capability for the purpose of promoting effective use of the frequency band. However, for coding rates greater than 3/4, a Viterbi decoder is impractical.
In the light of the above, there has been proposed an error correcting system which uses a coder and a decoder adapted for low coding rates and each having a relatively small hardware scale together with some simple additional peripheral circuits, as disclosed in Japanese Laid-Open Patent Publication (Kokai) No. 57-155857 (KDD) by way of example. With such circuits, this system transmits codes over a transmission path after increasing their coding rate so as to use code symbols of equivalently high rate. The hardware scale of the coder and decoder may be 1/2 while the coding rate on the transmission path may be as high as 7/8. Such a system achieves a sufficiently high error correcting capability. Further, the coder and decoder may be so constructed as to render a deleting pattern or map changeable. The changeable deleting pattern will implement an error correcting system having coding rates of 1/2, 3/4 and 7/8, for example.
A problem with the prior art decoder of an error correcting system of the kind described is as follows. The decoder performs code synchronization for the insertion of dummy bits and frequency division phase synchronization for the serial-to-parallel conversion of received data in which dummy bits are inserted, independently and on a trial-and-error basis. Hence, the total maximum necessary number of times of trials for both of code synchronization and frequency division phase synchronization is the product of the necessary maximum number of times of the individual synchronizations, resulting in an excessively long synchronization capture time.